EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
ExtremeTech

Researchers create CMOS-compatible, 30nm programmable graphene transistor

Electronic engineers at Japan's GNC and AIST research centers have successfully created graphene transistors that are constructed and operated in a way that redefines 50 years of transistor ...
Business Wire

Search For The Next: UK Collaboration Unveils Bizen® a Transistor Wafer Process Technology Promising to Slash Lead Times, Wafer Area and Process Layers While Increasing Speed ...

NOTTINGHAM, England--(BUSINESS WIRE)--A UK collaboration between Nottingham-based start-up, Search For The Next (SFN) and Glenrothes-based Semefab may be set to disrupt the semiconductor industry by ...
Electronic Design

Layout-Dependent Modeling Boosts CMOS Gate Density

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...