As system-on-chip (SoC) designs grow larger, designers must grapple with serious global timing problems, the effect of wire loading and timing delays and the performance hit associated with supporting ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

Instant Logic – just add keystrokes! HDK-0501 is the fastest way to get a digital logic circuit running, with an added bonus of controlling and interactively monitoring your circuit while it runs! HDK ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

In an era when power has become a fundamental design constraint, questions persist about whether asynchronous logic has a role to play. It is a design style said to have significant benefits and yet ...

Verification had always been an important part of SOC design flow. As SOCs are getting more and more complex, so is their verification. Verification of a design involves simulating the all possible ...

This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use ...

For the PDF version of this article, click here. The phase-shifted full bridge with current doubler output stage is a popular power supply topology in high-power and low-voltage, high-current ...

A synchronous computer has been developed that operates using the unique physics of moving water droplets. Their goal is to design a new class of computers that can precisely control and manipulate ...

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine ...