EDN

The CS4350 PLL DAC Simplifies System Design

Typical Digital to Analog Converters (DACs) require a high-speed Master Clock to clock their digital filters and modulators, as well as some portions of their discrete time analog circuitry. This ...
Design-Reuse

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a ...
EDN

PLL Subsystem architectures for SoC design

Because of the cornerstone importance of PLLs to an SoC design, this article considers the various challenges in the design of PLL subsystems, and discuss architectural solutions. The PLL subsystem is ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 2)

This is Part 2 of a three-part series. As discussed in Part 1 and recapped here, modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher ...
Design-Reuse

Specifying a PLL Part 2: Jitter Basics

No real clock sources (PLL’s, DLL’s, Crystal Oscillators, even function generators) exist that have a single, fixed value for their output period. The output period of all real clock sources changes ...
Electronic Design

How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers (Part 3)

A special technique produces very wide loop BWs in high-frequency PLLs (and hence, indirect (PLL) synthesizers), thereby achieving very low phase noise rivaling that of direct (MMD) synthesizers. A ...