New Electronics

Rambus launches HBM4E controller IP for next‑generation AI memory performance

Rambus has introduced a new HBM4E Memory Controller IP, marking what the company describes as a major step forward in meeting ...

Rambus targets AI memory bottlenecks with new HBM4E controller IP

The new HBM4E Controller builds on Rambus’s track record of more than 100 HBM design wins and the company’s long-standing focus on memory interface IP. The new controller incorporates advanced ...
Guru3D

Rambus ships HBM4E controller IP rated for 16 Gbps per pin

Rambus announced a new HBM4E memory controller IP block intended for next-generation AI accelerators, HPC processors, and graphics-oriented compute silicon. The controller is designed to support HBM4E ...
Design And Reuse

Rambus Sets New Benchmark for AI Memory Performance with Industry-Leading HBM4E Controller IP

Built on a proven track record of over one hundred HBM design wins to ensure first-time silicon success Delivers up to 16 Gigabits per second per pin at low latency to meet the demands of ...
Semiconductor Engineering

DRAM Simulator For Evaluation of Memory System Design Changes (ETH Zurich)

A technical paper titled “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator” was published by researchers at ETH Zurich. “We present Ramulator 2.0, a highly modular and extensible DRAM ...
Electronic Design

DDR FCRAM Boosts Performance In DDR SDRAM Designs

A modified form of synchronous DRAM technology, double-data-rate, fast-cycle random access memory (DDR FCRAM) is primarily focused at the networking market segment. Yet due to its high performance, it ...
EDN

PCI Express DMA Reference Design Using External Memory

The PCI Express DMA reference design using external memory highlights the performance of the Intel Arria V, Arria 10, Cyclone V and Stratix V Hard IP for PCI Express using the Avalon Memory-Mapped ...